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E2A0050-19-54 Semiconductor
Semiconductor ML7005
DTMF Transceiver
This version: May 1999 ML7005
GENERAL DESCRIPTION
The ML7005 is a multi-functional DTMF transceiver LSI with built-in a DTMF signal generator, a DTMF signal receiver, a call progress tone generator, a call progress tone detector, and a FAX (FX) signal detector. Each functional block can be controlled by an external MCU via a 4-bit processor interface. The ML7005 does not contains a modem. However, the DTMF system data transmission is possible at less than 66 bps by setting the DTMF receiver to the high-speed detection mode. The ML7005 operates with low-power consumption and is suitable for remote control systems, especially for ACR (Automatic Cost Routing) controllers.
FEATURES
* Wide range of power supply voltage : +2.7 V to +5.5 V * Low power consumption Operating mode : 4.0 mA (VDD = 3 V) Typ. Operating mode : 5.0 mA (VDD = 5 V) Typ. Power down mode : 1 mA Typ. * The 4-bit processor interface supports both the Intel processor mode in which a read signal and a write signal are used independently of each other, and the Motorola processor mode in which a read signal and a write signal are used in common. * The DTMF receiver can select either the high-speed detection mode (signal repeat time: more than 60 ms) or the normal detection mode (signal repeat time: more than 90 ms). * Built-in call progress tone generator * Built-in FAX signal (FX: 1300 Hz) detector * The DTMF signal generator, DTMF signal detector, call progress tone generator, and call progress tone detector can operate concurrently. * Built-in 3.579545 MHz crystal oscillator circuit * Package : 32-pin plastic SSOP (SSOP32-P-430-1.00-K) (Product name: ML7005MB)
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Semiconductor
ML7005
BLOCK DIAGRAM
FXDIM
- +
PRE LPF
FX Detector
FXD0
FXDIO CPDIP CPDIM CPDIO + - PRE LPF CPT Detector
CPD0
DTRIP DTRIM DTRIO
+ -
PRE LPF
DTMF Receiver
Control Register
DTGO DTAI - +
LPF
DTMF Generator
PTYPE D0 D1 Processor Interface D2 D3 READ WR ALE CS
DTAO CPTGO CPAI - + Status Register SG Generator CPT Generator
CPAO SG
X1
X2
VDD GND CLKO PD
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Semiconductor
PIN CONFIGURATION (TOP VIEW)

DTRIO 1 DTRIM DTRIP SG 2 3 4 5 6 7 8 9 CPAO CPAI CPTGO PTYPE VDD PD X1 X2 10 11 12 13 14 15 16 CLKO READ CS ALE
ML7005
32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17
CPDIO CPDIM CPDIP FXDIO FXDIM FXDO DTAO DTAI DTGO GND CPDO D0 D1 D2 D3 WR
32-Pin Plastic SSOP
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Semiconductor
ML7005
PIN DESCRIPTION
Pin 1 Symbol DTRIO Type O Description Output pin for DTMF signal receiver input amplifier. See the figure 8 for adjusting the receive signal level. See the figure 10 when the DTMF signal receiver is not used. Inverting input pin for DTMF signal receiver input amplifier. Non-inverting input pin for DTMF signal receiver input amplifier. Output pin for signal ground. The output voltage is half of VDD. Connect SG and GND by a 1 F capacitor. This pin goes to a high impedance state when in power down mode. Output pin for amplifier used for adjusting the transmit output level of CPT (Call Progress Tone) signal generator. The non-inverting input of this amplifier is internally connected to SG. See the figure 11 for adjusting the transmit signal level. When this amplifier is not used, the CPAO pin should be shorted to the CPAI pin. Inverting input pin for amplifier used to adjust the transmit level of the CPT signal generator. Analog output pin for CPT signal generator. The tone amplitude is approximately - 3 dBm. The transmit signal level can be changed by using the CPAO and CPAI pins. See the figure 11 for adjusting the transmit signal level. Control the ON/OFF of CPT transmission by using CPGC of the control register. Input pin for selecting the processor mode. This selection determines the functions of READ, CS, ALE, WR, D1 and D0 pins. When this pin is "1", the Intel processor mode is selected. When this pin is "0", the Motorola processor mode (MSM7524-compatible) is selected. This pin should be fixed at "0" or "1". Power supply pin. Input pin for controlling the power down mode. When this pin is set to "1", the entire LSI enters the power down mode and each functional operation stops. The DC level of the analog output pin becomes undefined. The digital output pins (FXD0, CPD0) and status register indicate a non-detection state. At that time, the control register CR and DTMF transmit register DTMFT are cleared. ("0" is written) The internal circuits (timer, etc. for each detector) also are reset. After turning on the power, set this pin to "1" to reset the LSI before using this LSI. When this pin is set to "0", the normal operation starts. X1 and X2 are connected to a 3.579545 MHz crystal. See "Oscillation Circuit" of the FUNCTIONAL DESCRIPTION for reference. 3.579545 MHz clock output pin. This pin can drive one ML7005 device.
2 3 4
DTRIM DTRIP SG
I I O
5
CPAO
O
6 7
CPAI CPTGO
I O
8
PTYPE
I
9 10
VDD PD
-- I
11 12 13
X1 X2 CLKO
I O O
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Semiconductor
ML7005
Pin 14
Symbol READ
Type I
Description Input pin for processor interface. When PTYPE is "1" (Intel processor mode) : This pin is the read control input pin. When this pin is set to "0", data in the specified register is output to the bus lines (D3 to D0). At that time, CS must be "0". See the figure 4 for processor interface timing. When PTYPE is "0" (Motorola processor mode) : This pin is the clock input pin (equivalent to SCLK of the MSM7524). When in Write mode, data in D3 to D0 is written to the specified register at the falling edge of the READ signal. When in Read mode, data in the specified register is output to D3 to D0 when the READ signal is "1", and D3 to D0 should be open when the READ signal is "0". The READ signal is not necessarily a periodical signal. See the figure 5 for processor interface timing. Chip select input pin for processor interface. When the CS signal is "0", read and write operations are possible. When the CS signal is "1", read and write operations are impossible. Input pin for processor interface. When PTYPE is "1" (Intel processor mode) : This pin is the address latch enable input pin. The register address data in D1 to D0 is latched at the falling edge of ALE. When PTYPE is "0" (Motorola processor mode) : This pin is the address data input pin (equivalent to AD0 of the MSM7524). When this pin is "1", data can be written to the control register (CR) and data can be read from the status register (STR). When this pin is "0", data can be written to the DTMF transmit register (DTMFT) and data can be read from the DTMF receive register (DTMFR). Input pin for processor interface. When PTYPE is "1" (Intel processor mode) : This pin is the Write control input. Data in the data bus lines (D3 to D0) is written to the specified register. At that time, CS must be "0". When PTYPE is "0" (Motorola processor mode) : This is the signal input pin for controlling the Read and Write modes (equivalent to R/W of the MSM7524). When this pin is "1", the LSI enters the Read mode. When this pin is "0", the LSI enters the Write mode. 4-bit data bus I/O pins for processor interface. When PTYPE is "1" (Intel processor mode), D1 and D0 are also used for addressing. Digital output pin for CPT detector. When a 400 Hz signal is input to the CPDIP and CPDIM pins, this pin is "1". When the DOEN register is "0", this pin is fixed at "0". Ground pin. Analog output pin for DTMF signal generator. The tone amplitude is approximately - 9.0 dBm for a low group and approximately - 7.0 dBm for a high group. The transmit signal level can be changed by using the DTAI and DTAO pins. See the figure 11 for adjusting the transmit signal level. Control the ON/OFF of signal transmission by using MFC of the control register.
15
CS
I
16
ALE
I
17
WR
I
18 - 21 D3 - D0 22 CPDO
I/O O
23 24
GND DTGO
-- O
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Semiconductor
ML7005
Pin 25
Symbol DTAI
Type I
Description Inverting input pin for operational amplifier used for adjusting the transmit output level of the DTMF signal generator. The non-inverting input of this amplifier is internally connected to SG. See the figure 11 for adjusting the transmit signal level. When this amplifier is not used, the DTAO pin should be shorted to the DTAI pin. Output pin for operational amplifier used for adjusting the transmit output level of the DTMF signal generator. Digital output pin for FAX signal (FX) detector. When a 1300 Hz signal is input to the FXDIM, this pin is "1". When a call progress tone (CPT) is received (CPD0="1"), this pin is forced to be "0". When the DOEN register is "0", this pin is fixed at "0". Inverting input pin for input amplifier used for detecting the FAX signal (FX). See the figure 9 for adjusting the receive signal level. When the FX detector is not used, the FXDIM pin should be shorted to the FXIO pin. Output pin for input amplifier used for detecting the FAX signal (FX). Non-inverting input pin for input amplifier used for detecting the CPT. See the figure 8 for adjusting the receive signal level. When the CPT detector is not used, see the figure 10. Inverting input pin for input amplifier used for detecting the CPT. Output pin for input amplifier used for detecting the CPT.
26 27
DTAO FXDO
O O
28
FXDIM
I
29 30
FXDIO CPDIP
O I
31 32
CPDIM CPDIO
I O
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Semiconductor
ML7005
ABSOLUTE MAXIMUM RATINGS
Parameter Power Supply Voltage Input Voltage Storage Temperature Output Short Current Power Dissipation Symbol VDD VI Tstg ISHT PD Condition Ta = 25C With respect to GND -- Short to VDD or GND -- Rating -0.3 to +7.0 -0.3 to VDD + 0.3 -55 to +150 35 100 Unit V C mA mW
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Operating Temperature Range Input Clock Frequency Deviation Input Clock duty X1, X2 Load Capacitance SG Bypass Capacitance VDD Bypass Capacitance Digital Input Rise Time Digital Input Fall Time Digital Ouput Load Capacitance Frequency Deviation
Crystal
Symbol VDD TOP fCLK DUTY C1, C2 C3 C4 C5 TIR TIF CDL1 CDL2 -- -- -- -- SG - GND X1
Condition -- -- An external clock is applied to -- VDD - GND PD, READ, CS, ALE, WR, C3 to D0 FCDO, CPDO, D3 to D0 CLKO +25C 5C -30C to +85C -- --
Min. 2.7 -30 -0.1 40 18 1 10 0.1 -- -- -- -- -100 -100 -- --
Typ. 3.6 -- -- -- 20 -- -- -- -- -- -- -- -- -- -- 16
Max. 5.5 +85 +0.1 60 22 -- -- -- 50 50 40 20 +100 +100 90 --
Unit V C % % pF mF
ns pF ppm W pF
Temperature Characteristics Equivalent Series Resistance Load Capacitance
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Semiconductor
ML7005
ELECTRICAL CHARACTERISTICS
DC and Digital Interface Characteristics
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter Symbol Condition or Applicable pin IDD1 Power Supply Current IDD2 Digital Input Voltage Digital Input Current Digital Output Voltage VIH VIL IIH IIL VOH VOL VOHCK VOLCK Analog Input Resistance Analog Output DC Potential Analog Output Load Resistance RIN VSG VAO ROUT VI = VDD VI = 0 V Other than CLK0 IOL = -100 mA VDD = 2.7 to 5.5 V Operating Mode VDD = 3 V VDD = 5 V Power Down Mode -- Min. -- -- -- -- 0.7 VDD 0.0 -10 -10 0.0 VDD - 0.5 0.0 -- -- 20 Typ. -- 4.0 5.0 1 -- -- 0 0 0.06 -- -- 10 VDD/2 -- Max. 9.0 -- -- 40 VDD 0.3VDD +10 +10 VDD 0.2 VDD 0.5 -- -- -- MW V KW V mA V mA mA Unit
IOH = -100 mA VDD - 0.2 VDD - 0.06
CLKO, CL 20pF *1 SG *2 *3
VDD /2-0.1 VDD/2 VDD /2-0.1
*1 DTRIM, DTRIP, CPAI, DTAI, FXDIM, CPDIP, CPDIM *2 DTRIO, CPAO, CPTGO, DTGO, DTAO, FXDIO, CPDIO *3 DTRIO, CPAO, CPTGO, DTGO, DTAO, FXDIO, CPDIO, SG
AC CHARACTERISTICS
AC Characteristics 1 DTMF Signal Generator
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter DTMF Tone Transmit Amplitude Tone Transmit Amplitude Ratio Tone Frequency Accuracy Total Harmonic Distortion Symbol VDTTL VDTTH VDTDF fDDT THDDT VS1 Out-of-Band Spurious VS2 VS3 Measured at DTGO Condition Low Group Tone High Group Tone VDTTH - VDTTL To Nominal Frequency Harmonics Fundamental With respect to 4kHz to 8kHz output signal at DTGO 8kHz to 12kHz 4 kHz band level measured 12 kHz to each Min. -10.5 -8.5 1.0 -1.5 -- -- -- -- Typ. -9.0 -7.0 2.0 -- -40 P-51 P-60 P-75 Max. -7.5 -5.5 3.0 +1.5 -23 P-20 P-40 P-60 dB Unit dBm dB % dB *1
*1 0dBm = 0.775 Vrms (For all AC characteristics)
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Semiconductor AC Characteristics 2 Call Progress Tone (CPT) Generator
ML7005
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter Tone Transmit Amplitude Output Frequency Total Harmonic Distortion Symbol VCPT fCPT THDCPT Condition -- -- Harmonics - Fundamental Min. -4 380 -- Typ. -2.5 400 -39 Max. -1 420 -23 Unit dBm Hz dB
AC Characteristics 3 Call Progress Tone (CPT) Detector
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter CPT Detect Amplitude CPT Non-detect Amplitude Time to Detect Time to Reject CPT Detect Delay Time CPT Detect Hold Time CPT Detect Frequency CPT Non-detect Frequency Symbol VDETCP VREJCP tDETCP tREJCP tDELCP tHOLCP fDETCP fRETCP Condition 2.7 V VDD 5.5 V 4.5 V VDD 5.5 V fin = 350 to 450 Hz at CPDIO Detect Non-detect See Figure 1. -- -- Min. -46 -46 -- 30 -- 10 10 350 530 -- Typ. -- -- -- -- -- 18 18 -- -- -- Max. -6 0 -60 -- 10 30 30 450 -- 290 ms ms Hz Hz dBm Unit
tREJCP CPDI
tDETCP
tDELCP CPDO (CPDR)
tHOLCP
Figure 1 CPT Detect Timing
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Semiconductor AC Characteristics 4 FAX Signal (FX) Detector
ML7005
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter FX Detect Amplitude FX Non-detect Amplitude Time to Detect Time to Reject FX Detect Delay Time FX Detect Hold Time FX Detect Frequency FX Non-detect Frequency Symbol VDETFX VREJFX tDETFX tREJFX tDELFX tHOLFX fDETFX fREJFX Condition 2.7 V VDD 5.5 V 4.5 V VDD 5.5 V fin = 1280 to 1320 Hz at FXDIO Detect Non-detect See Figure 2. -- -- Min. -40 -40 -- 65 -- 35 35 1280 1380 -- Typ. -- -- -- -- -- 50 50 -- -- -- Max. -6 0 -60 -- 30 65 65 1320 -- 1200 Hz Hz ms dBm Unit
tREJFX FXDI
tDETFX
tDELFX FXDO (FXDR)
tHOLFX
Figure 2 FX Detect Timing
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Semiconductor AC Characteristics 5 DTMF Receiver
ML7005
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter DTMF Detect Amplitude DTMF Non-detect Amplitude Detect Frequency Non-detect Frequency Level Twist Noise to Signal Ratio Dial Tone Rejection Ratio Signal Repetition Time Time to Detect Time to Reject Interdigit Pause Time Symbol VDETDT1 VDETDT2 VREJDT fDETDT fREJDT VTWIST VN/S VREJDT tCYCDT0 tCYCDT1 tRETDT0 tRETDT1 tREJDT0 tREJDT1 tPOSDT0 tPOSDT1 tBRKDT10 Acceptable Drop Out Time tBRKDT11 tBRKDT20 tBRKDT21 Detect Delay Time Detect Hold Time SP Delay Time tDELDT0 tDELDT1 tHOLDT0 tHOLDT1 tSP *1 SP = "1" SP = "0" Detect Non-detect To Nominal Frequency VHigh Group - VLow Group N/S (N : 0.3 to 3.4 kHz) 360 to 440 Hz DTTIM = "1" DTTIM = "0" DTTIM = "1" DTTIM = "0" DTTIM = "1" DTTIM = "0" DTTIM = "1" DTTIM = "0" DTTIM = "1" DTTIM = "1" DTTIM = "1" DTTIM = "0" DTTIM = "1" DTTIM = "0" DTTIM = "1", "0"
(Before output) DTTIM = "0" (During output) DTTIM = "0"
Condition 2.7 V VDD 5.5 V 4.5 V VDD 5.5 V Per Frequency at DTRIO
Min. -44 -44 -- -1.8 3.8 -- -6.0 -- -- 60 90 35 49 -- -- 21 30 -- -- -- -- 12 24 15 24 0.2
Typ. -- -- -- -- -- -- -- -12 45 -- -- -- -- -- -- -- -- -- -- -- -- 26 41 20 28 0.6
Max. -10 0 -60 +1.8 -- -3.8 +6.0 -- -- -- -- -- -- 10 24 -- -- 0.4 0.4 3 10 37 49 27 35 1.0
Unit dBm
%
dB
ms
*1 See the figure 3 for timing. The input level includes the entire range indicated in VDETDT1 and VDETDT2. The input frequency includes the entire range indicated in fDETDT.
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Semiconductor Timing When DTMF is received
tBRKDT1 tCYCDT tREJDT tDETDT tPOSDT tBRKDT2
ML7005
AIN Signal
tDELDT
DTMF Receive Data
tHOLDT
SP
tSP
Figure 3 Timing When DTMF is Received
tDETDT : Time to Detect When Time to Detect is the specified value of tDETDT or more, the DTMF signal is normally received. tREJDT : Time to Reject When Time to Reject is the specified value of tREJDT or less, the input signal is ignored and the SP and DTMF receive data are not output. tPOSDT : Interdigit Pause When there is no input signal for the period of tPOSDT or more, the DTMF receive data and SP are reset. Even if the receive data is changed, when Interdigit Pause Time is the value of tPOSDT or less (including the change without Drop Out), SP remains at "0" and the DTMF receive data may maintain its initial value. tBRKDT1 : Acceptable Drop Out Time 1 Acceptable Drop Out Time 1 is applied between when the input signal comes and when SP becomes "0". Even if there is no input signal for the period of tBRKDT1 or less, the SP and DTMF receive data are normally output. tBRKDT2 : Acceptable Drop Out Time 2 Acceptable Drop Out Time 2 is applied when SP is "0" (when receive data is output). Even if there is no input signal during signal reception for the period of tBRKDT2 or less, SP and DTMF receive data are not reset. tCYCDT : Signal Repetition Time Signal Repetition Time should be the specified value of tCYCDT or more so that a signal is normally received. tDELDT : Detect Delay Time The DTMF receive data is output with a delay of the specified value of tDELDT after the input signal appears. tHOLDT : Detect Hold Time The SP and DTMF receive data outputs stop with a delay of the specified value of tHOLDT after the input signal disappears. tSP : SP Delay Time The SP data is output with a delay of the specified value of tSP after the DTMF receive data is output. The DTMF receive data should be latched after detecting the fall of SP.
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Semiconductor Processor Interface Charactceristics (Intel Processor Mode)
ML7005
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter Address Data Setup Time Address Data Hold Time ALE Signal Time Chip Select Setup Time before Read Chip Select Hold Time after Read READ Data Output Delay Time Data Float Time after Read READ Signal Time
Chip Select Setup Time before Write
Symbol tAL tLA tLL tCRS tCRH tRD tRDF tRW tCWS tCWH tWW tDW tWD
Condition -- -- -- -- -- VOL 0.4 V, VOH VDD - 0.4 V -- -- -- -- -- -- --
Min. 80 30 80 30 30 0 5 200 30 30 140 80 30
Typ. -- -- -- -- -- 90 37 -- -- -- -- -- --
Max. -- -- -- -- -- 180 60 -- -- -- -- -- --
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns
Chip Select Hold Time after Write WR Signal Time Data Setup Time before Write Data Hold Time
tLL ALE tRW READ WR tAL D0 to D3 CS tLA tRD tRDF
READ DATA
tLL
tWW
tAL
tLA
tDW tWD
WRITE DATA
ADDRESS
ADDRESS
tCRS
tCRH
tCWS
tCWH
Figure 4 Processor Interface Timing (Intel Processor Mode : PTYPE="1")
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Semiconductor Processor Interface Characteristics (Motorola Processor Mode)
ML7005
(VDD = 2.7 to 5.5 V, Ta = -30 to +85C) Parameter READ Signal Period READ Signal Pulse Width ALE CS WR D3 to D0 (Write) D3 to D0 (Read) Hold Time tDRH SETUP Time HOLD Time SETUP Time HOLD Time SETUP Time HOLD Time SETUP Time HOLD Time Delay Time Symbol tCYC tHI tLO tAS tAH tCS tCH tWRS tWRH tDWS tDWH tDRD
See
Condition -- "H" period "L" period ALE AE READ READ AE ALE CS AE READ READ AE CS WR AE READ D3 to D0 AE READ READ AE D3 to D0 READ AE D3 to D0 VOL 0.4 V, VOH VDD - 0.4 V D3 to D0 AE READ
Figure 5 READ AE WR
Min. 1 200 200 80 20 80 20 80 20 80 30 0 5
Typ. -- -- -- -- -- -- -- -- -- -- -- 90 37
Max. -- -- -- -- -- -- -- -- -- -- -- 180 60
Unit ms
ns
tCYC tHI READ (Clock) ALE (Address) tCS CS WR (Read / Write) tWRS tWRH tWRS tCH tCS tLO tHI
tCYC tLO
tAS
tAH
tAS
tAH
tCH
tWRH
tDWS D3 to D0 DATA "Write"
tDWH
tDRD DATA "Read"
tDRH
Figure 5 Processor Interface Timing (Motorola Processor Mode)
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Semiconductor
ML7005
REGISTER DESCRIPTION
Register Interface Description The ML7005 contains a 4-bit DTMF transmit data register (DTMFT), a 4-bit DTMF receive data register (DTMFR), a 4-bit control register (CR), and a 4-bit status register (STR). The DTMFT and CR registers are for Write-only and the DTMFR and STR registers are for Read-only. When the PTYPE pin is "1", accessing the registers is possible in the Intel processor mode. When the PTYPE pin is "0", accessing the registers is possible in the Motorola processor mode. In the Intel processor mode (PTYPE="1"), when CS is "0", data can be written to the DTMFT and CR registers by fetching data from D3 to D0 at the rising edge of the WR signal. When CS is "0", the contents of DTMFR and STR can be transferred to D3 to D0 by setting READ to "0". In the Motorola processor mode (PTYPE="0"), when CS and WR are "0", data can be written to the DTMFT and CR registers by fetching D3 to D0 data and ALE at the falling edge of READ. When CS is "0" and WR is "1", the contents of DTMFR and STR are transferred to D3 to D0 by latching ALE at the rising edge of READ. When the PD pin is set to "1" the DTMFT and CR registers are reset. Table 1 Outline of Registers
Accessing (address) in Intel processor mode D1 DTMFT DTMFR CR STR 0 0 1 1 D0 0 1 0 1 Accessing in Motorola processor mode ALE 0 0 1 1 WR 0 1 0 1 Writing to DTMFT Reading from DTMFR Writing to CR Reading from STR
Register name
Description
Note:
The contents of the DTMFT and CR registers cannot be read. Table 2 Register Names
Register name DTMFT DTMFR CR STR D3 DTT3 DTR3 CPGC SP D2 DTT2 DTR2 DTTIM FXDR D1 DTT1 DTR1 DOEN CPDR D0 DTT0 DTR0 MFC DETF
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Semiconductor DTMFT and DTMFR Registers
ML7005
16 kinds of DTMF transmit signals can be determined by setting the DTMFT register. 16 kinds of DTMF receive signals can be monitored from the DTMFR register. The table 3 shows the DTMF signal codes. Even if the DTMF transmit code is changed while the DTMF signal is being transmitted (MFC="1"), the output frequency is not changed. Table 3 DTMF Signal Code List
DTT3 DTR3 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 0 DTT2 DTR2 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 0 DTT1 DTR1 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 DTT0 DTR0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 DIGIT 1 2 3 4 5 6 7 8 9 0 * # A B C D Low group signal (Hz) 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 941 High group signal (Hz) 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 1633
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Semiconductor Control Register CR
D3 CPGC Bit No. D3 D2 DTTIM Name CPGC D1 DOEN D0 MFC Description This bit is used to control the ON/OFF of call progress tone transmitting. "0" : The GPTGO output is OFF and the SG level is output. "1" : The GPTGO output is ON and CPT is output.
ML7005
D2
DTTIM
This bit is used to control the detect time of DTMF receiver. "0" : Normal detect "1" : High-speed detect When there is enough time, set to the normal detect mode (DTTIM = "0") because the high-speed detect mode sometimes causes erroneous detection by noise or voice signal. This bit is used to control the call progress tone detector and FX detector. "0" : The CPDO and FXDO output pins and CPDR and FXDR registers are fixed to "0". "1" : The CPDO and FXDO output pins and CPDR and FXDR registers become valid. This bit is used to control the ON/OFF of DTMF transmit output. "0" : The DTGO output is OFF and the SG level is output. "1" : The DTGO output is ON and the DTMF signal is output.
D1
DOEN
D0
MFC
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Semiconductor Status Register STR
D3 SP Bit No. D3 Name SP D2 FXDR D1 CPDR D0 DETF Description This bit is used to indicate whether the DTMF receive signal is being received. "0" : Indicates that the valid DTMF signal is being received. "1" : Indicates that the DTMF signal is not being received. This bit is used to indicate whether the FAX signal (FX) is being received. "0" : Indicates that the FAX signal (FX) is not being received. "1" : Indicates that the valid FAX signal (FX: 1300 Hz) is being received. When a call progress tone is received (CPDO="1"), this bit is forced to be "0". When the DOEN register is "0", this bit also is fixed at "0". This bit has the same function as that of the FXDO.
ML7005
D2
FXDR
D1
CPDR
This bit is used to indicate whether the call progress tone is being received. "0" : Indicates that the call progress tone is not being received. "1" : Indicates that the valid call progress tone (400 Hz) is being received. When the DOEN register is "0", this bit is fixed at "0". This bit has the same function as that of the CPDO pin. This is a flag to indicate that a detector has changed its status from a non-detect state to a detect state. This bit is "1" when: (1) SP is changed from "1" to "0", (2) FXDR is changed from "0" to "1", or (3) CPDR is changed from "0" to "1". This bit remains "0" even if a 1300 Hz or 400 Hz signal is input, because the FXDR and CPDR are fixed at "0" when the DOEN regsiter is "0". When the processor has read the status register, this bit is reset to "0". When the processor does not read the status register after a signal is detected, this bit is "0" after the detected signal disappears.
D0
DETF
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Semiconductor
ML7005
FUNCTIONAL DESCRIPTION
Oscillation Circuit The X1 and X2 should be connected by a 3.579545 MHz crystal. When the load capacitance of the crystal is 16pF, X1 and GND should be connected by a 20 pF capacitor, and X2 and GND also should be connected by a 20 pF capacitor. If necessary, an external clock should be input to X1 via a 1000 pF capacitor, and X2 should be left open.
C1 X1 3.579545MHz X2 X2 3.579545MHz X1
C2
Figure 6 Crystal Connection
Figure 7 External Clock Connection
DTMF Receiver, CPT Detector Input Level Adjustment Adjust the input level according to the method shown in the figure 8. Determine the value of a usable resistor so that the levels of the outputs (DTIO, CPDIO) of each amplifier at a maximum input level are less than the maximum detect level described in the AC Characteristics.
CA IN
DTRIP DTRIM DTRIO RB
(CPDIP) (CPDIM) (CPDIO)
+ -
DTRIO RE CA IN RD DTRIM DTRIP
(CPDIO)
(CPDIM) (CPDIP) Gain =
- + RE 10 RD
RA
RC SG
R Gain = 1 + B 10 RC SG
RA 100 kW RB, RC 50 kW CA 0.1 mF
Figure 8 DTMF, CPT Input Level Adjustment
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Semiconductor FX Detector Input Level Adjustment
ML7005
Adjust the input level according to the method shown in the figure 9. Determine the value of a usable resistor so that the output level of FXDIO is less than the maximum detect level described in the AC Characteristics.
FXDIO RG C8 IN RF FXDIM RG 10 RF
- +
Gain =
Figure 9 FX Input Level Adjustment Processing the Input Pin when the DTMF Receiver and CPT Detector are not Used Process the Input pin according to the method shown in the figure 10.
DTRIO (CPDIO)
DTRIM (CPDIM) DTRIP (CPDIP)
- +
SG
Figure 10 Processing the Unused Input Pin
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Semiconductor Adjusting the Analog Output Level
ML7005
Adjust the analog output level according to the method shown in the figure 11. RI/RH 1.6 is always required when VDD 4.5 V. In the case of RI /RH > 1, if RI /RH = A, the maximum analog output load resistance is 20*A (kW). If VDD is less than 4.5 V, RI/RH 1 is required.
DTGO (CPDGO) Generator RH DTAI (CPAI) - + RI DTAO (CPAO) OUT Gain = RI RH
Figure 11 Analog Output Level Adjustment
Concurrent Operation of 4 Functions The DTMF signal generator, DTMF signal detector, call progress tone generator, and call progress tone detector can operate concurrently. When both the DTMF signal generator and call progress tone generator operate concurrently, the DTMF signal sometimes cannot be detected if the receive level of the DTMF signal is less than -36 dBm.
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Semiconductor Register Settings for Each Mode An example of register settings for each mode is shown below. Table 4 Register Setting
Address in Motorola Intel processor processor mode mode ALE WR D1, D0 -- -- -- -- 10 10 11 11 01 11 11 10 11 11 11 00 10 -- 10 -- -- 10 -- 10 -- -- -- -- 1 1 1 1 0 1 1 1 1 1 1 0 1 -- 1 -- -- 1 -- 1 -- -- -- -- 0 0 1 1 1 1 1 0 1 1 1 0 0 -- 0 -- -- 0 -- 0
ML7005
Mode
Description
D3
D2
D1
D0
Active register
Power ON
(1) Wait until power supply is stabilized (2) PD pin = "1" (internal circuit is reset) (3) Wait 200 ms or more (4) PD pin = "0" (5) CR setting
-- -- -- -- X 0 1 0 X 0 1 0 1 1 1 X 0 -- 0 -- -- 1 -- 0
-- -- -- -- X 1 0 0 X 0 0 0 0 0 0 X 0 -- 0 -- -- 0 -- 0
-- -- -- -- X 0 0 0 X 0 0 1 0 1 1 X 0 -- 0 -- -- 0 -- 0
-- -- -- -- X 0 0 1 X 0 0 0 0 1 0 X 1 -- 0 -- -- 0 -- 0
-- -- -- -- CR CR STR STR DTMFR STR STR CR STR STR STR DTMFT CR -- CR -- -- CR -- CR
DTMF Detect (1) Detect timing setting (High Speed) (2) STR monitoring (when not detected) (3) STR monitoring (when detected) (4) DTMF receive data reading (5) STR monitoring (when
detected and after reading STR)
(6) STR monitoring (after making the input signal OFF) CPT Detect (1) CPT detect enable setting (2) STR monitoring (when not detected) (3) STR monitoring (when detected)
(4) STR monitoring (when detected and after reading STR)
DTMF Transmit
(1) DTMF transmit data setting (2) DTMF transmit ON (3) Wait transmit ON time (4) DTMF transmit OFF (5) Wait transmit OFF time (6) To transmit next data, return to (1)
CPT Transmit (1) CPT transmit ON (2) Wait transmit ON time (3) CPT transmit OFF
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Semiconductor
ML7005
APPLICATION CIRCUIT EXAMPLE
ML7005
R1 1 C6 DTMF Input R2 2 3 4 C3 5 6 7 8 +2.7 to 5.5 V C4 9 + - C5 10 C1 C2 11 3.579545 MHz 12 13 14 15 16
DTRIO DTRIM DTRIP SG CPAO CPAI CPTGO PTYPE VDD
CPDIO CPDIM CPDIP FXDIO FXDIM FXDO DTAO DTAI DTGO GND
32 R3 31 30 29 R5 28 27 26 25 24 23 22 21 20 19 18 17 To MPU R6 C8 FX Input R4 C7 CPT Input
PD X1 X2 CLKO READ CS ALE
CPDO D0 D1 D2 D3 WR
Note :
indicates connection to the SG pin.
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Semiconductor
ML7005
PACKAGE DIMENSIONS
(Unit : mm)
SSOP32-P-430-1.00-K
Mirror finish
Package material Lead frame material Pin treatment Solder plate thickness Package weight (g)
Epoxy resin 42 alloy Solder plating 5 mm or more 0.60 TYP.
Notes for Mounting the Surface Mount Type Package The SOP, QFP, TSOP, TQFP, LQFP, SOJ, QFJ (PLCC), SHP, and BGA are surface mount type packages, which are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person on the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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E2Y0002-29-11
NOTICE
1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents cotained herein may be reprinted or reproduced without our prior permission. MS-DOS is a registered trademark of Microsoft Corporation.
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Copyright 1999 Oki Electric Industry Co., Ltd.
Printed in Japan

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